Welcome to Verilog-to-Routing’s documentation!

https://www.verilogtorouting.org/img/des90_placement_macros.gif https://www.verilogtorouting.org/img/des90_nets.gif https://www.verilogtorouting.org/img/des90_routing_util.gif

For more information on the Verilog-to-Routing (VTR) project see VTR and VTR CAD Flow.

For documentation and tutorials on the FPGA architecture description language see: FPGA Architecture Description.

For more specific documentation about VPR see VPR.

Indices and tables