Odin II

Odin II is used for logic synthesis and elaboration, converting a subset of the Verilog Hardware Description Language (HDL) into a BLIF netlist.

Note

Odin-II has been deprecated and will be removed in a future version. Now VTR uses Parmys as the default frontend which utilizes Yosys as elaborator with partial mapping features enabled.

To build the VTR flow with the Odin-II front-end you may use the VTR Makefile wrapper, by calling the make CMAKE_PARAMS="-DWITH_ODIN=ON" command in the $VTR_ROOT directory.

Quickstart

• Quickstart
  • Prerequisites
  • Building
  • Basic Usage
  • Example Usage

User Guide

• User guide
  • Synthesis Arguments
  • Simulation Arguments
  • Examples
  • Getting Help
  • Reporting Bugs and Feature Requests

verilog Support

• Verilog Support
  • Lexicon
  • Syntax

Developer Guide

• Contributing
  • Creating a Pull Request (PR)
  • Odin II’s Flow
  • Useful tools of Odin II for Developers
• Regression Tests
  • Benchmarks
  • Creating Regression Tests
  • Regression Test Summaries
• Verify Script
  • Arguments
  • Examples
• TESTING ODIN II
  • USING MODELSIM TO TEST ODIN II