VTR CAD Flow

Fig. 1 illustrates the CAD flow typically used in VTR.

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    splines=ortho;

    #Files
    node [shape=Mrecord, style=filled, fillcolor="/greys4/1:/greys4/2", gradientangle=270, fontname="arial", width=3];
    verilog_file[label="Behavioural Circuit\nDescription (Verilog HDL)", group=g1];
    odin_blif[label="BLIF Netlist\n(logic, flip-flops, blackboxes)", group=g1];
    opt_blif[label="Optimized BLIF Netlist\n(LUTs, flip-flops, blackboxes)", group=g1];
    arch[label="FPGA Architecture\nDescription (XML)"];
    pnr_files[label="Pack, Place, Route\nOutput Files", group=g1];
    report_files[label="Reports and Statistics"];
    existing_pnr_files[label="Existing Pack, Place, Route Files\n(from VPR or other tools)", style="dashed,filled"];

    #Tools
    node [shape=record, fillcolor="/blues4/2:/blues4/3"];
    odin[label="ODIN\n(Front-end Synthesis)", group=g1];
    abc[label="ABC\n(Logic Optimization,\nTechnology Map to LUTs)", group=g1];

    subgraph cluster_vpr {
        style="filled,solid";
        color="/blues4/2:/blues4/3";
        gradientangle=270;
        node [style=filled,color=white];

        vpr[label="VPR", group=g1, shape=plaintext, style=""];
        vpr_pack[label="Packing", group=g1];
        vpr_place[label="Placement", group=g1];
        vpr_route[label="Routing", group=g1];
        vpr_analysis[label="Analysis", group=g1];

        vpr -> vpr_pack[style=invis];
        vpr_pack -> vpr_place -> vpr_route -> vpr_analysis;
    }

    #Edges
    arch -> odin:w;
    verilog_file -> odin -> odin_blif;
    odin_blif -> abc -> opt_blif;

    arch -> vpr:w [lhead=cluster_vpr];
    opt_blif -> vpr [lhead=cluster_vpr];

    vpr_analysis -> pnr_files [ltail=cluster_vpr];
    vpr_analysis -> report_files [ltail=cluster_vpr];

    existing_pnr_files -> vpr [style=dashed, lhead=cluster_vpr];
}

Fig. 1 Typical VTR CAD Flow

First, Odin II converts a Verilog Hardware Destription Language (HDL) design into a flattened netlist consisting of logic gates and blackboxes which represent heterogeneous blocks [JKGS10].

Next, the ABC synthesis package is used to perform technology-independent logic optimization, and then technology-maps the circuit into LUTs and flip-flops [SG][PHMB07][CCMB07]. The output of ABC is a .blif format netlist of LUTs, flip flops, and blackboxes.

VPR then packs this netlist into more coarse-grained logic blocks, places and then routes the circuit [BRM99][Bet98][BR96a][BR96b][BR97b][BR97a][MBR99][MBR00][BR00]. Generating output files for each stage. VPR will analyze the resulting implementation, producing various statistics such as the minimum number of tracks per channel required to successfully route, the total wirelength, circuit speed, area and power.

CAD Flow Variations

Many variations on this CAD flow are possible. It is possible to use other high-level synthesis tools to generate the blif files that are passed into ABC. Also, one can use different logic optimizers and technology mappers than ABC; just put the output netlist from your technology-mapper into .blif format and feed it into VPR.

Alternatively, if the logic block you are interested in is not supported by VPR, your CAD flow can bypass VPR’s packer by outputting a netlist of logic blocks in .net format. VPR can place and route netlists of any type of logic block – you simply have to create the netlist and describe the logic block in the FPGA architecture description file.

If you want only to route a placement produced by another CAD tool you can create a .place file, and have VPR route this pre-existing placement.

If you want only to analyze an implementation produced by another tool with VPR, you can create a .route file, and have VPR analyze the implementation, to produce area/delay/power results.

Finally, if your routing architecture is not supported by VPR’s architecture generator, you can create an rr_graph.xml file, which can be loaded directly into VPR.