Welcome to Verilog-to-Routing’s documentation!
For more information on the Verilog-to-Routing (VTR) project see VTR and VTR CAD Flow.
For documentation and tutorials on the FPGA architecture description language see: FPGA Architecture Description.
For more specific documentation about VPR see VPR.
Quick Start
Usage
- VTR
- VTR CAD Flow
- Get VTR
- Building VTR
- Optional Build Information
- Running the VTR Flow
- Benchmarks
- Power Estimation
- Server Mode
- Interactive Path Analysis Client (IPA)
- Tasks
- run_vtr_flow
- run_func_sim_flow
- run_vtr_task
- parse_vtr_flow
- parse_vtr_task
- Parse Configuration
- Pass Requirements
- VTR Flow Python library
- FPGA Architecture Description
- VPR
- Parmys
- Odin II
- ABC
- Tutorials
- Utilities
Development
- Developer Guide
- Contribution Guidelines
- Commit Procedures
- Commit Messages and Structure
- Code Formatting
- Sanitizing Includes
- Running Tests
- Evaluating Quality of Result (QoR) Changes
- Adding Tests
- Debugging Aids
- Speeding up the edit-compile-test cycle
- Speeding Compilation
- Profiling VTR
- External Subtrees
- Finding Bugs with Coverity
- Release Procedures
- Sphinx API Documentation for C/C++ Projects
- Documenting VTR Code with Doxygen
- Developer Tutorials
- Coding Style
- VTR Support Resources
- VTR License
- VTR Change Log
Appendix
API Reference