Verilog-to-Routing Logo
latest

Quick Start

  • VTR Quick Start

Usage

  • Building VTR
  • VTR
  • FPGA Architecture Description
  • VPR
  • Odin II
  • Yosys+Odin-II
    • Quickstart
    • User guide
    • Verilog Support
    • Developers Guide
      • Contributing
      • Yosys+Odin-II’s Flow
      • Regression Tests
      • Testing Yosys+Odin-II
  • Yosys
  • ABC
  • Tutorials
  • Utilities

Development

  • Developer Guide
  • VTR Change Log

Appendix

  • Contact
  • Glossary
  • Publications & References

API Reference

  • VPR API
  • VTRUTIL API
Verilog-to-Routing
  • Docs »
  • Yosys+Odin-II »
  • Developers Guide
  • Edit on GitHub

Developers Guide¶

  • Contributing
  • Yosys+Odin-II’s Flow
    • Yosys Elaboration
    • BLIF Reader and Building the Netlist
    • BLIF Elaboration
    • Partial Technology Mapping
    • Simulator
  • Regression Tests
    • Benchmarks
    • Creating Regression Tests
    • Yosys+Odin-II Task Structure
    • Yosys+Odin-II Suite Structure
    • Regenerating Results
    • Yosys+Odin-II Regression Tests Directory Tree
  • Testing Yosys+Odin-II
Next Previous

© Copyright 2016, VTR Developers Revision e6c20492.

Built with Sphinx using a theme provided by Read the Docs.
Read the Docs v: latest
Versions
latest
stable
v8.0.0
Downloads
pdf
html
epub
On Read the Docs
Project Home
Builds
Free document hosting provided by Read the Docs.