There are several sets of benchmark designs which can be used with VTR.
The VTR benchmarks [RLY+12][LAK+14] are a set of medium-sized benchmarks included with VTR. They are fully compatible with the full VTR flow. They are suitable for FPGA architecture research and medium-scale CAD research.
The VTR benchmarks are provided as Verilog under:
This provides full flexibility to modify and change how the designs are implemented (including the creation of new netlist primitives).
The VTR benchmarks are also included as pre-synthesized BLIF files under:
The Titan benchmarks are suitable for large-scale FPGA CAD research, and FPGA architecture research which does not require synthesizing new netlist primitives.
The Titan benchmarks are not included with the VTR release (due to their size). However they can be downloaded and extracted by running
make get_titan_benchmarks from the root of the VTR tree. They can also be downloaded manually.
The MCNC benchmarks [Yan91] are a set of small and old (circa 1991) benchmarks. They consist primarily of logic (i.e. LUTs) with few registers and no hard blocks.
The MCNC20 benchmarks are not recommended for modern FPGA CAD and architecture research. Their small size and design style (e.g. few registers, no hard blocks) make them unrepresentative of modern FPGA usage. This can lead to misleading CAD and/or architecture conclusions.
The MCNC20 benchmarks included with VTR are available as
.blif files under:
The versions used in the VPR 4.3 release, which were mapped to \(K\)-input look-up tables using FlowMap [CD94], are available under:
|Benchmark||Approximate Number of Netlist Primitives|