FPGA Architecture Description

VTR uses an XML-based architecture description language to describe the targeted FPGA architecture. This flexible description language allows the user to describe a large number of hypothetical and commercial-like FPGA architectures.

An interactive visualizer is available for exploring VTR FPGA architecture description files. It provides a device-wide, inter-tile grid view and a detailed intra-tile view of primitives and local interconnect, as well as many other views, making it easier to develop and debug architecture XML files without running the full VPR flow.

• Web application (no install required): Open in Browser

• Source code and native binaries (Windows, Linux, macOS): GitHub Repository

See the Architecture Modeling for an introduction to the architecture description language. For a detailed reference on the supported options see the Architecture Reference.

• Architecture Reference
  • Top Level Tags
  • Recognized BLIF Models (<models>)
  • Global FPGA Information
  • FPGA Grid Layout
  • FPGA Layer Information
  • FPGA Device Information
  • Switches
  • Physical Tiles
  • Complex Blocks
  • NoC Description
  • Wire Segments
  • Clocks
  • Power
  • Direct Inter-block Connections
  • Custom Switch Blocks
  • Scatter-Gather Patterns
  • Architecture metadata
  • Additional Syntax for Tileable Architecture
• Example Architecture Specification