Contexts¶

Classes¶

class VprContext : public Context ¶

This object encapsulates VPR’s state.

There is typically a single instance which is accessed via the global variable g_vpr_ctx (see globals.h/.cpp).

It is divided up into separate sub-contexts of logically related data structures.

Each sub-context can be accessed via member functions which return a reference to the sub-context:

The default the member function (e.g. device()) return an const (immutable) reference providing read-only access to the context. This should be the preferred form, as the compiler will detect unintentional state changes.
The ‘mutable’ member function (e.g. mutable_device()) will return a non-const (mutable) reference allowing modification of the context. This should only be used on an as-needed basis.

Typical usage in VPR would be to call the appropriate accessor to get a reference to the context of interest, and then operate on it.

For example if we were performing an action which required access to the current placement, we would do:

void my_analysis_algorithm() {
    //Get read-only access to the placement
    auto& place_ctx = g_vpr_ctx.placement();

    //Do something that depends on (but does not change)
    //the current placement...

}

If we needed to modify the placement (e.g. we were implementing another placement algorithm) we would do:

void my_placement_algorithm() {
    //Get read-write access to the placement
    auto& place_ctx = g_vpr_ctx.mutable_placement();

    //Do something that modifies the placement
    //...
}

Note: The returned contexts are not copyable, so they must be taken by reference.

Structures¶

struct AtomContext : public Context ¶

State relating to the atom-level netlist.

This should contain only data structures related to user specified netlist being implemented by VPR onto the target device.

Public Members

AtomNetlist nlist¶: Atom netlist.

AtomLookup lookup¶: Mappings to/from the Atom Netlist to physically described .blif models.

struct ClusteringContext : public Context ¶

State relating to clustering.

This should contain only data structures that describe the current clustering/packing, or related clusterer/packer algorithmic state.

Public Members

ClusteredNetlist clb_nlist¶: New netlist class derived from Netlist.

struct Context¶

A Context is collection of state relating to a particular part of VPR.

This is a base class who’s only purpose is to disable copying of contexts. This ensures that attempting to use a context by value (instead of by reference) will result in a compilation error.

No data or member functions should be defined in this class!

Subclassed by AtomContext, ClusteringContext, DeviceContext, PlacementContext, PlacerContext, PlacerMoveContext, PlacerRuntimeContext, PlacerTimingContext, PowerContext, RoutingContext, TimingContext, VprContext

struct DeviceContext : public Context ¶

State relating the device.

This should contain only data structures describing the targeted device.

Public Members

DeviceGrid grid¶: FPGA complex block grid [0 .. grid.width()-1][0 .. grid.height()-1].

bool has_multiple_equivalent_tiles¶: Boolean that indicates whether the architecture implements an N:M physical tiles to logical blocks mapping.

t_chan_width chan_width¶: chan_width is for x|y-directed channels; i.e. between rows

std::vector<t_rr_rc_data> rr_rc_data¶: Fly-weighted Resistance/Capacitance data for RR Nodes.

std::vector<std::vector<int>> rr_non_config_node_sets¶: Sets of non-configurably connected nodes.

std::unordered_map<int, int> rr_node_to_non_config_node_set¶: Reverse look-up from RR node to non-configurably connected node set (index into rr_nonconf_node_sets)

t_rr_node_indices rr_node_indices¶: The indicies of rr nodes of a given type at a specific x,y grid location.

std::vector<t_rr_switch_inf> rr_switch_inf¶: Autogenerated in build_rr_graph based on switch fan-in. [0..(num_rr_switches-1)].

std::vector<t_segment_inf> rr_segments¶: Wire segment types in RR graph.

int virtual_clock_network_root_idx¶

rr_node idx that connects to the input of all clock network wires

Useful for two stage clock routing XXX: currently only one place to source the clock networks so only storing a single value

MetadataStorage<int> rr_node_metadata¶

Attributes for each rr_node.

key: rr_node index value: map of <attribute_name, attribute_value>

MetadataStorage<std::tuple<int, int, short>> rr_edge_metadata¶

Attributes for each rr_edge.

key: <source rr_node_index, sink rr_node_index, iswitch> iswitch: Index of the switch type used to go from this rr_node to the next one in the routing. OPEN if there is no next node (i.e. this node is the last one (a SINK) in a branch of the net’s routing). value: map of <attribute_name, attribute_value>

std::vector<std::map<int, int>> switch_fanin_remap¶

switch_fanin_remap is only used for printing out switch fanin stats (the -switch_stats option)

array index: [0..(num_arch_switches-1)]; map key: num of all possible fanin of that type of switch on chip map value: remapped switch index (index in rr_switch_inf)

std::string read_rr_graph_filename¶

Name of rrgraph file read (if any).

Used to determine when reading rrgraph if file is already loaded.

struct PlacementContext : public Context ¶

State relating to placement.

This should contain only data structures that describe the current placement, or related placer algorithm state.

Public Members

vtr::vector_map<ClusterBlockId, t_block_loc> block_locs¶: Clustered block placement locations.

vtr::vector_map<ClusterPinId, int> physical_pins¶: Clustered pin placement mapping with physical pin.

vtr::Matrix<t_grid_blocks> grid_blocks¶: Clustered block associated with each grid location (i.e. inverse of block_locs)

std::vector<t_pl_macro> pl_macros¶: The pl_macros array stores all the placement macros (usually carry chains).

t_compressed_block_grids compressed_block_grids¶

Compressed grid space for each block type.

Used to efficiently find logically ‘adjacent’ blocks of the same block type even though the may be physically far apart

std::string placement_id¶

SHA256 digest of the .place file.

Used for unique identification and consistency checking

struct PowerContext : public Context ¶

State relating to power analysis.

This should contain only data structures related to power analysis, or related power analysis algorithmic state.

Public Members

std::unordered_map<AtomNetId, t_net_power> atom_net_power¶: Atom net power info.

struct RoutingContext : public Context ¶

State relating to routing.

This should contain only data structures that describe the current routing implementation, or related router algorithmic state.

Public Members

vtr::dynamic_bitset non_configurable_bitset¶

Information about whether a node is part of a non-configurable set.

(i.e. connected to others with non-configurable edges like metal shorts that can’t be disabled) Stored in a single bit per rr_node for efficiency bit value 0: node is not part of a non-configurable set bit value 1: node is part of a non-configurable set Initialized once when RoutingContext is initialized, static throughout invocation of router

t_net_routing_status net_status¶: Information about current routing status of each net.

vtr::vector<ClusterNetId, t_bb> route_bb¶: Limits area within which each net must be routed.

std::string routing_id¶

SHA256 digest of the .route file.

Used for unique identification and consistency checking

vtr::Cache<std::tuple<e_router_lookahead, std::string, std::vector<t_segment_inf>>, RouterLookahead> cached_router_lookahead_¶

Cache of router lookahead object.

Cache key: (lookahead type, read lookahead (if any), segment definitions).

struct TimingContext : public Context ¶

State relating to timing.

This should contain only data structures related to timing analysis, or related timing analysis algorithmic state.

Public Members

std::shared_ptr<tatum::TimingGraph> graph¶

The current timing graph.

This represents the timing dependencies between pins of the atom netlist

std::shared_ptr<tatum::TimingConstraints> constraints¶

The current timing constraints, as loaded from an SDC file (or set by default).

These specify how timing analysis is performed (e.g. target clock periods)