Verilog-to-Routing
v8.0.0
Usage
VTR
FPGA Architecture Description
VPR
Odin II
ABC
Tutorials
Design Flow Tutorials
Architecture Modeling
Running the Titan Benchmarks
Post-Implementation Timing Simulation
Utilities
Development
Developer Guide
VTR Change Log
Appendix
Contact
Glossary
Publications & References
Verilog-to-Routing
Docs
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Tutorials
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Tutorials
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Design Flow Tutorials
Basic Design Flow Tutorial
Architecture Modeling
Classic Soft Logic Block Tutorial
Configurable Memory Bus-Based Tutorial
Fracturable Multiplier Bus-Based Tutorial
Fracturable Multiplier Example
Configurable Memory Block Example
Virtex 6 like Logic Slice Example
Primitive Block Timing Modeling Tutorial
Running the Titan Benchmarks
Integrating the Titan benchmarks into VTR
Running benchmarks manually
Post-Implementation Timing Simulation
Generating the Post-Implementation Netlist
Inspecting the Post-Implementation Netlist
Creating a Test Bench
Performing Timing Simulation in Modelsim