Running the VTR Flow¶
VTR is a collection of tools that perform the full FPGA CAD flow from Verilog to routing.
The design flow consists of:
Parmys (Logic Synthesis & Partial Mapping)
ABC (Logic Optimization & Technology Mapping)
VPR (Pack, Place & Route)
There is no single executable for the entire flow.
Instead, scripts are provided to allow the user to easily run the entire tool flow. The following provides instructions on using these scripts to run VTR.
Running a Single Benchmark¶
The run_vtr_flow script is provided to execute the VTR flow for a single benchmark and architecture.
In the following $VTR_ROOT means the root directory of the VTR source code tree.
$VTR_ROOT/vtr_flow/scripts/run_vtr_flow.py <circuit_file> <architecture_file>
It requires two arguments:
<circuit_file>A benchmark circuit, and
<architecture_file>an FPGA architecture file
Circuits can be found under:
Architecture files can be found under:
The script can also be used to run parts of the VTR flow.
run_vtr_flow for the detailed command line options of
Running Multiple Benchmarks & Architectures with Tasks¶
VTR also supports tasks, which manage the execution of the VTR flow for multiple benchmarks and architectures. By default, tasks execute the run_vtr_flow for every circuit/architecture combination.
VTR provides a variety of standard tasks which can be found under:
Tasks can be executed using run_vtr_task:
run_vtr_task for the detailed command line options of
Tasks for more information on creating, modifying and running tasks.
Extracting Information & Statistics¶
VTR can also extract useful information and statistics from executions of the flow such as area, speed tool execution time etc.
For single benchmarks parse_vtr_flow extrastics statistics from a single execution of the flow.
For regression testing purposes these results can also be verified against a set of golden reference results. See parse_vtr_task for details.